Double Data Rate (DDR) memories are popular due to their performance and density. However, to reduce a size of the memory, control of the memory has been offloaded to circuits known as DDR memory controllers. These controller circuits can be located in different places, such as integrated into a processor or a stand-alone Application Specific Integrated Circuit (ASIC) positioned between the processor and the memory.
For accessing memories, such as dynamic random access memory (DRAM), error correction codes (ECCs) can be used to protect against errors and data corruption. In addition, data within the memory can be encrypted. To read the data, the ECC decode occurs first, together with a potential correction of the data due to an ECC error, and then a decryption is performed of the decoded data. Such a process results in latency to perform memory reads and can impact the system performance.